In many logic, memory and timing arrangements, it is necessary to communicate between functional blocks which require different drive voltages. Voltage level shifters provide interfaces where the voltage levels available at the output of one block do not meet the voltage level requirements of an interconnected block.
U.S. Pat. No. 4,618,785 (H. van Tran) discloses a CMOS differential sense amplifier which includes n-channel level shifters and a differential sense amplifier. The level shifters use only n-channel transistors and thus lose a threshold voltage when providing an output high (a "1") signal. The sense amplifier uses complementary MOS transistors and can perform a level shifting function. It is unable to provide an output voltage level below the same low voltage level associated with the level shifter which has an output coupled to an input of the differential sense amplifier.
While the design of voltage level shifters is well known in the art, there are often special operating conditions and device characteristics that cause poor operation of known circuits. For example, flat panel displays (e.g., liquid crystal displays) often require special interface circuits to discharge transistors having very large time constants. Where the circuits are formed on a glass panel using thin film techniques, the thin film device (e.g., field effect transistor) characteristics are not as precisely defined as bulk type devices. In such apparatus, the proper operation must be assured over a wide range of conditions and a wide range of device parameters. It is desired to have a voltage level shifter circuit which is adapted to operate with widely varying device characteristics and is suitable for implantation using CMOS thin film transistors on the glass of a liquid crystal display.